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Interrupts and events
Table 53.
Vector table for other STM32F10xxx devices (continued)
RM0008
Type of
priority
Acronym
Description
Address
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
settable
settable
settable
settable
settable
settable
settable
settable
settable
settable
settable
settable
settable
settable
settable
settable
settable
settable
settable
settable
settable
settable
settable
settable
settable
SPI1
SPI2
USART1
USART2
USART3
EXTI15_10
RTCAlarm
USBWakeup
TIM8_BRK
TIM8_UP
TIM8_TRG_COM
TIM8_CC
ADC3
FSMC
SDIO
TIM5
SPI3
UART4
UART5
TIM6
TIM7
DMA2_Channel1
DMA2_Channel2
DMA2_Channel3
DMA2_Channel4_5
SPI1 global interrupt
SPI2 global interrupt
USART1 global interrupt
USART2 global interrupt
USART3 global interrupt
EXTI Line[15:10] interrupts
RTC alarm through EXTI line
interrupt
USB wakeup from suspend through
EXTI line interrupt
TIM8 Break interrupt
TIM8 Update interrupt
TIM8 Trigger and Commutation
interrupts
TIM8 Capture Compare interrupt
ADC3 global interrupt
FSMC global interrupt
SDIO global interrupt
TIM5 global interrupt
SPI3 global interrupt
UART4 global interrupt
UART5 global interrupt
TIM6 global interrupt
TIM7 global interrupt
DMA2 Channel1 global interrupt
DMA2 Channel2 global interrupt
DMA2 Channel3 global interrupt
DMA2 Channel4 and DMA2
Channel5 global interrupts
0x0000_00CC
0x0000_00D0
0x0000_00D4
0x0000_00D8
0x0000_00DC
0x0000_00E0
0x0000_00E4
0x0000_00E8
0x0000_00EC
0x0000_00F0
0x0000_00F4
0x0000_00F8
0x0000_00FC
0x0000_0100
0x0000_0104
0x0000_0108
0x0000_010C
0x0000_0110
0x0000_0114
0x0000_0118
0x0000_011C
0x0000_0120
0x0000_0124
0x0000_0128
0x0000_012C
9.2
174/995
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of up to 20 edge detectors in connectivity line
devices, or 19 edge detectors in other devices for generating event/interrupt requests. Each
input line can be independently configured to select the type (pulse or pending) and the
corresponding trigger event (rising or falling or both). Each line can also masked
independently. A pending register maintains the status line of the interrupt requests
Doc ID 13902 Rev 9
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